The present invention relates to a photolithographic process. More particularly, the present invention relates to a photolithographic process that employs a sandwich photoresist structure.
As the level of integration of integrated circuits increases, dimensions of devices within the integrated circuits must be reduced. Photolithographic processes are important in the manufacturing of metal-oxide-semiconductor (MOS) related devices. For example, the patterning of thin film layers and the formation of doped regions involve photolithographic processes. However, many problems are encountered as device dimensions are reduced. The miniaturization of devices is often limited by current resolution of the photolithographic process. Furthermore, the reduction of device dimensions also increases the probability of having alignment errors. To match up with the required miniaturization, methods for increasing the resolution of photomask and processes having self-aligning capacity have been developed.
Conventional methods for increasing resolution include such techniques as phase shift mask (PSM) photolithography and optical proximity correction (OPC). However, all these methods target an improvement in the design of photomask and rarely aim at the design of photoresist structure.
In general, misalignment is highly probable when a device is miniaturized. A dual damascene structure is particularly vulnerably to a misalignment problem due to the separate formation of a trench and a via opening using two masks. At present, a number of self-aligned processes have already been developed, but none of them suggests a self-aligned method that uses a sandwich photoresist structure to form a dual damascene structure.